In contemporary digital circuit applications, quite often either CMOS or ECL signals are implemented to effect logic levels both within the chip and off chips. Further, many circuits utilize both ECL and CMOS signals. Accordingly, there exists a need for a circuit and method for translating CMOS signals to suitable ECL counterparts. The CMOS to ECL conversion carries with it a propagation delay for both high to low and low to high signal transitions. Accordingly, it is desirable to provide an efficient CMOS to ECL translator which causes a minimum propagation delay as a result of signal transitions.
A prior art circuit for translating CMOS signals to ECL signals has been heretofore constructed utilizing a CMOS inverter which drives the base of a bipolar junction transistor (BJT). This prior art configuration provides a CMOS to ECL conversion control signal which is converted to an ECL output signal. The propagation delay associated with the high to low transition of the output signal is on the order of 500 to 600 picoseconds. However, the propagation delay during the low to high transition of the ECL output signal is considerably slower for this prior art configuration. Therefore, a need has arisen for a circuit and methodology for providing CMOS to ECL translation such that the propagation delay associated with both low to high transitions and high to low transitions is minimized.